The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 07, 1993

Filed:

Sep. 04, 1992
Applicant:
Inventors:

Jayasimha S Prasad, Tigard, OR (US);

Song W Park, Aloha, OR (US);

William A Vetanen, Sherwood, OR (US);

Irene G Beers, Sherwood, OR (US);

Curtis M Haynes, Portland, OR (US);

Assignee:

Tektronix, Inc., Wilsonville, OR (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 31 ; 437 59 ; 437 60 ; 437133 ; 148D / ;
Abstract

The disclosed HBT IC process can fabricate npn heterojunction bipolar transistors, Schottky diodes, MIM capacitors, spiral inductors, and NiCr resistors. Two levels of interconnect metal are available. The first level metal is a conventional dielectric-insulated metal conductor. The second level metal includes an air-bridge for contacting the HBT emitters, which are on top of three level mesa structures. It is also an advanced low loss, low capacitance, air dielectric conductor useful for long interconnects and inductors. MIM capacitors are formed by sandwiching silicon nitride between the first layer metal and a capacitor top plate made with landed air-bridge metal. Precision thin film resistors are fabricated by depositing NiCr on silicon nitride. The three-level active mesa structure is etched down to the GaAs substrate, for lateral device isolation, with a truncated pyramidal shape which permits good step coverage of dielectric and metallization layers. The wet etching process uses a composition of H.sub.3 PO.sub.4 :H.sub.2 O.sub.2 :H.sub.2 O in a preferred ratio of about 3:1:25 for the AlGaAs/GaAs system.


Find Patent Forward Citations

Prasad, Jayasimha. (1993). Implant-free heterojunction bioplar transistor integrated circuit process (U.S. Patent No. 5268315). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5268315

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