Dynamic memory having access transistor turn-off state

Abstract

A dynamic memory having improved cell access transistor turn-off state. In order to reduce subthreshold leakage current through cell access devices, the wordline signal voltage is alternates between V.sub.CC (the access transistor turn-on voltage) and a negative potential, rather than between V.sub.CC and ground potential. By applying a negative potential to the wordline during the period when the cell access transistor is required to be in an 'off' state, V.sub.GS is made more negative, which results in more complete turn off of the access transistor during the period when the cell capacitor is storing charge. The negative potential replaces ground potential as the pull-down voltage input for signal-inverting wordline drivers. The negative potential may be derived from an existing charge pump used to negatively backbias the substrate, or it may be derived from a dedicated charge pump. However, in order to eliminate the potential problem of current injection, the two negative voltages should be approximately equal. In order to implement the preferred embodiment of this invention, a masked adjustment implant is performed so that the V.sub.T of N-channel cell access transistors within the memory array remains unchanged, while the V.sub.T of the wordline driver N-channel pull-down transistors is raised by an amount substantially equal to V.sub.BB, the backbias voltage.