The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 1993

Filed:

May. 05, 1992
Applicant:
Inventors:

Gregory Hindman, Boise, ID (US);

Jack Berg, Boise, ID (US);

Peter N Manos, II, Boise, ID (US);

Assignee:

Zilog, Inc., Campbell, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437190 ; 437192 ; 437200 ; 20419217 ;
Abstract

The present invention concerns a method for contact metallization on a semiconductor where a contact hole is formed in an interlevel dielectric layer down to a doped silicon region on the silicon substrate, and then the wafer is placed into a sputtering chamber where titanium is sputtered onto the wafer. A titanium nitride layer is sputtered on top of the titanium layer in the contact hole. This invention saves time and money, because the titanium nitride layer depositing and titanium layer forming steps can occur in the same chamber without forming the boro-phosphorous silicate glass layer in between. The titanium layer reacts with the silicon to form a silicide layer at the time of the sputtering in a hot deposition or in later steps that supply heat to the wafer for a period of time. Optionally, an additional titanium layer can be formed on top of the titanium nitride layer to clean off the titanium target used to sputter the titanium and titanium nitride layers on the wafer. A metal layer including aluminum is then formed on top of the titanium layer or the titanium nitride layer to form the contact metallization with the doped silicon region in the semiconductor.


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