The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 03, 1993

Filed:

Oct. 13, 1992
Applicant:
Inventors:

Masakuni Tokita, Nagano, JP;

Akira Kobayashi, Nagano, JP;

Shinichi Yamakawa, Nagano, JP;

Mitsuharu Shimizu, Nagano, JP;

Norihiro Masuda, Nagano, JP;

Assignees:

Shinko Electric Industries Co., Ltd., Nagano, JP;

Intel Corp., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B32B / ; H05K / ;
U.S. Cl.
CPC ...
29830 ; 29 2501 ; 29429 ; 156261 ;
Abstract

A process for manufacturing a multi-layer lead frame for a semiconductor device comprises two metal plains being adhered to each other via an insulation piece. An insulation strip is punched to cut the insulation piece, which is preliminary adhered to a metal strip. The metal strip is then punched to cut and remove the metal plane, which is then laminated and heat-pressed to another metal strip. After completely adhered, the other metal strip is punched to remove a multi-layer lead frame.


Find Patent Forward Citations

Tokita, Masakuni. (1993). Process for manufacturing a multi-layer lead frame (U.S. Patent No. 5231756). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5231756

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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