The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 29, 1993
Filed:
Nov. 25, 1991
Warren M Uesato, San Jose, CA (US);
Kwang-Leei K Young, Palo Alto, CA (US);
Hung-Kwei Hu, Saratoga, CA (US);
Paul K Aum, Austin, TX (US);
Hewlett-Packard Company, Palo Alto, CA (US);
Abstract
During the manufacture of a semiconductor integrated circuit, contact holes or passages are formed through a non-planar insulating layer resulting from the deposition of dielectric over electrical contacts having differing profile heights from the surface of an internal layer, such as a substrate, to expose these contacts and/or provide electrical connections thereto. The passages are formed with a combination of sloped and vertical sidewall portions in which varying depth sloped portions are used to effectively planarize the dielectric layer and permit the vertical sidewall portions to have substantially identical vertical dimensions. This technique simultaneously exposes contacts with varying profile heights which thereby reduces contact damage. In addition, this technique effectively planarizes the dielectric layer, reducing the need for an additional planarization step.