Process and system for stabilizing layer deposition and etch rates while

Abstract

Extraneous and undesirable particulate matter is suppressed in a reaction chamber for treating semiconductor materials by depositing a thin layer of polymeric or equivalent insulating material over the entire interior surfaces of the reaction chamber prior to any treatment therein of semiconductor wafers or the like. This process is repeated as necessary after the initial treatment of the wafers has begun, and this treatment will typically include the layer deposition and layer etching on the surfaces of the semiconductor wafers. The periodic intervals between subsequent polymer layer deposition within the reaction chamber is selected in proportion to measured etch or deposition rates therein to thereby optimize the stability and uniformity of these etch and deposition rates, while simultaneously maintaining a maximum degree of cleanliness within the reaction chamber and minimizing down time therefor. The above control of particulate tack-down film deposition may be carried out using a novel closed loop control system in which etch and film deposition rates are measured to generate an error signal, and this error signal is used to control a gas flow controller which in turn regulates the frequency of tack-down film deposition within the reaction chamber.