The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 11, 1993

Filed:

Dec. 12, 1991
Applicant:
Inventors:

Been-Jon K Woo, Saratoga, CA (US);

Gregory Atwood, San Jose, CA (US);

Stefan K Lai, Belmont, CA (US);

T C Ong, San Jose, CA (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 43 ; 148D / ; 148D / ;
Abstract

A process for fabricating an electrically programmable read-only memory array having increased density includes forming recessed field oxide regions in a silicon substrate. Elongated parallel wordline stacks are then formed over the surface of the substrate. Source and drain regions are formed by ion implantation in the openings between these vertical stacks. These openings are then filled with a metal layer until the wafer is substantially planar. This metal layer is then patterned to form drain contact pads and V.sub.SS interconnect strips. The V.sub.SS interconnect strips contact adjacent source regions across field oxide regions that insulate adjacent memory cells.


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