System timing analysis by self-timing logic and clock paths

Abstract

A system and method of determining the propagation delay between LSSD (Level Sensitive Scan Delay) latch pairs is performed by modifying system and scan clock sequences. A set bit is initially scanned to the input of the sending trigger. This is done by inhibiting the last B clock. These A and B clocks are then gated off and the system clocks operate a complete cycle with the unique sequence of inhibiting the first latch pulse and the last trigger pulse. Finally, a unique scan clock sequence is used to scan out data from the receiving latch. If the data scanned out corresponds with expected data (the set bit), the process is repeated decreasing the cycle time of the system clocks until the set bit is no longer received. The measured delay is then taken as the preceding cycle time. By measuring the delays between a plurality of points and a common originating point and taking the differences in these delays, the skew in a clock distribution system can be readily determined.