Method of making electrically erasable and electrically programmable

Abstract

A method of forming a doped region within a monocrystalline silicon layer of an integrated circuit having an electrically erasable and electrically programmable memory device on a semiconductor substrate, wherein the doped region lies within a channel region near a drain region, but does not lie within a source region. After a patterned layer is formed over the channel region, the substrate is doped by ion implantation with a first dopant at a tilt angle no less than a minimum tilt angle and at about a predetermined azimuthal angle, such that a significant number of ions enter a drain region and a channel region near the drain region and substantially no ions enter a source region. The first dopant is the same dopant type as the monocrystalline silicon layer dopant. The drain region is masked. The source region is doped with a second dopant. The second dopant is an opposite dopant type as the monocrystalline silicon layer dopant. The source region and the drain region are doped with a third dopant. The third dopant is the same dopant type as the second dopant. The third dopant dose is heavier than the first dopant dose, and the second dopant diffusion coefficient is greater than the third dopant diffusion coefficient.