The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 1992
Filed:
Apr. 02, 1991
Chih-Liang Chen, Briarcliff, NY (US);
Peter W Cook, Mount Kisco, NY (US);
Lewis M Terman, South Salem, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An ECL circuit (12) for directly coupling to and from a CMOS circuit (10). The ECL circuit has an input node for receiving an input signal generated by a CMOS circuit. The input signal swings, or transitions, between a first potential (V.sub.0) and a second potential (V.sub.1). The ECL circuit further includes ECL core circuitry (Q.sub.3, Q.sub.4, R.sub.L), coupled to the input node and responsive the received signal, for generating an intermediate electrical signal that swings between a third potential (V.sub.2) and a fourth potential (V.sub.3) that is approximately two times (V.sub.1 -V.sub.0). The ECL circuit further includes an output driver circuit for coupling to an input of a CMOS circuit or to another ECL circuit. The output driver circuit has an input node coupled to an output of the ECL core circuitry and includes emitter followers (EF.sub.1, EF.sub.2) for generating, in response to the intermediate electrical signal swinging between V.sub.2 and V.sub.3, a first output signal tha swings between the V.sub.0 and V.sub.1.