The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 1992

Filed:

Jun. 07, 1991
Applicant:
Inventors:

Ragupathy V Giridhar, San Jose, CA (US);

Philip E Freiberger, Santa Clara, CA (US);

Brian A Kaiser, Redwood City, CA (US);

Yi-Ching Lin, Sunnyvale, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
437195 ; 437238 ; 437247 ;
Abstract

A method of forming a device having an intermetal dielectric film which is formed and annealed to prevent a significant quantity of ambient moisture from being absorbed by the intermetal dielectric film prior to passivation layer deposition is disclosed. An intermetal dielectric layer is formed over a substrate having a interconnection layer. A second interconnect layer is formed over the IMD layer. The substrate with the intermetal dielectric is annealed anytime between IMD formation and passivation layer deposition to produce a film that does not absorb a significant quantity of ambient moisture, and therefore, longer queue times can be utilized between the anneal and subsequent processing. The present invention reduces the amount of water in the device which reduces hot electron induced device degradation.


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