The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 14, 1992
Filed:
Aug. 07, 1989
Philip E Freiberger, Santa Clara, CA (US);
Leopoldo D Yau, Portland, OR (US);
Cheng-Sheng Pan, Sunnyvale, CA (US);
George E Sery, San Franciso, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A method and a device formed by the method of forming a composite dielectric structure between the floating polysilicon electrode and the control electrode of an EPROM-type device is disclosed. The dielectic is characterized by a thin (0-80 angstroms) thermally-grown or CVD bottom oxide layer covered by a relatively thin (<200 angstroms) silicon nitride layer. The top layer comprises a CVD oxide deposited in a thickness up to 150 angstroms. The capacitively measured effective thickness of the complete structure is about 200 .ANG. or less. The top layer CVD oxide has a thickness greater than the bottom oxide layer and greater than or equal to that of the silicon nitride layer and may also extend beyond the EPROM cell to form at least a part of the peripheral transistor dielectric.