Method for improving device scalability of buried bit line flash eprom

Abstract

A process for fabricating contactless electrically programmable and electrically erasable memory cells of the flash EPROM type. The cells use elongated source and drain regions disposed beneath field oxide regions. A high quality tunnel oxide is grown on the channel regions of the device, followed by deposition of a polysilicon buffer layer. The use of the polysilicon buffer layer results in short reoxidation beaks. The field oxide is grown in a short, low temperature wet oxidation step, enhanced by the presence of heavy dopant implants. The use of a short, low temperatue oxide growth allows the use of thin nitride masking members and results in short reoxidation beaks as well as less stress on the substrate during field oxide growth. Also, since a low temperature field oxidation is used, the quality of the tunnel oxide will be maintained. The thin nitride masking members are removed in a wet etch process which does not degrade the underlying polysilicon buffer layer. Therefore, the polysilicon buffer layer does not need to be removed and remains as part of the device. Since the polysilicon buffer layer is not removed, there is no damage to the underlying tunnel oxide, and this layer remains on the device as well. Because these layers remain after field oxide growth, there is no tunnel oxide growth subsequent to the field oxide growth as with prior art processes. Therefore, the reoxidation beak does not continue to grow during tunnel oxide growth as occurs with prior art processes where the tunnel oxide is grown after field oxide growth. Also, the dopant implanted regions are subjected to fewer thermal cycles than in prior art processes, resulting in shallower junctions. In addition, since the tunnel oxide is grown before the implantation of dopants, the quality of this layer is better than conventional tunnel oxides grown in the presence of dopant. The short reoxidation beak, reduced thermal cycles and better tunnel oxide quality of the present invention results in a greater effective channel length at a given drawn dimension, allowing for improved scaling and increased device density.