Data output buffer circuit for a sram

Abstract

For a SRAM having a sense amplifier amplifying memory data and a read/write control circuit controlling operations of the sense amplifier, a data output buffer circuit is provided, which includes: a drive output node from which data output buffer provides output data; a first circuit providing a NOR function of an SAS signal from the sense amplifier and an output enable signal (OE) from the read/write control circuit; a second circuit providing a NOR function of an SAS signal from the sense amplifier and the output enable signal (OE) from the read/write control circuit; a third circuit eliminating noise produced by transition in the outputs of the first and second circuit and also enhancing a response time; a fourth circuit inverting the output of the first circuit; a fifth circuit inverting twice, sequentially, the output of the second circuit; and a sixth circuit responsive to the fourth and fifth circuit, alternatively providing, depending on the SAS and an SAS signal from the sense amplifier, one of three states on the drive output node: a first and second output state, and a third high impedance state. None of the first, second, third, fourth, fifth, and sixth circuit requires use of a single pulse output signal externally provided to the data output buffer circuit. During transition from the first state to the second state, the drive output node passes through the third high impedance state.