Electrically erasable programmable read-only memory with nand

Abstract

An erasable programmable read-only memory with a NAND cell structure including NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and memory cell transistors connected is series. Word lines are connected to control gates of the cell transistors. In a data write mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive to connect the cell block to the corresponding bit line. A control circuit is provided for applying an 'L' Level voltage (approximately O V) to a word line connected to the selected cell, applying an 'H' level voltage (approximately 20 V) to a word line or word lines positioned between the selected word line and a contact node connecting the cell block and a specific bit line associated therewith, applying a voltage corresponding to data to be written to the specific bit line, and applying an intermediate voltage between the 'H' and 'L' level voltages to non-selected bit lines, thereby writing the data in the selected cell by tunneling. If the data is logic '0' data, the intermediate voltage is applied also to the specific bit line.