The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 23, 1991
Filed:
Feb. 07, 1989
Yasuo Ohba, Yokohama, JP;
Yukie Nishikawa, Narashino, JP;
Hajime Okuda, Yokohama, JP;
Masayuki Ishikawa, Tokyo, JP;
Hideto Sugawara, Tokyo, JP;
Hideo Shiozawa, Yokohama, JP;
Yoshihiro Kokubun, Yokohama, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
A semiconductor laser device using double heterostructure comprised of In.sub.x Ga.sub.y Al.sub.1-x-y P (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1), capable of preventing the leakage of the carriers and thereby reducing the threshold current, being operative with small threshold current density and at high temperature, and having a long lifetime. The device may include a double heterostructure formed on the GaAs substrate, comprised of In.sub.x Ga.sub.y Al.sub.1-x-y P (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1) including an active layer, the active layer having an impurity concentration not greater than 5.times.10.sup.16 cm.sup.-3. The device may include a double heterostructure formed on the GaAs substrate, comprised of InGaP active layer and p-type In.sub.q (Ga.sub.1-z Al.sub.z).sub.q P (0.ltoreq.q.ltoreq.1, 0.ltoreq.z.ltoreq.1) cladding layer with a value of z between 0.65 and 0.75. The device may include a double heterostructure formed on the GaAs substrate, comprised of In.sub.x Ga.sub.y Al.sub.1-x-y P (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1) including an n-type cladding layer and an p-type cladding layer, one of the n-type cladding layer and the p-type cladding layer being Si-doped. A method of manufacturing the device is also disclosed.