The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 25, 1991
Filed:
Nov. 21, 1989
Chin S Park, Sunnyvale, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An apparatus and method for improved reading/programming of a virtual ground EPROM array includes a selected memory cell within the array which is accessed so as to avoid parasitic current flow in adjacent cells by first selecting the row line coupled to the control gate electrode of the selected cell. Next, a first column line coupled to the source of the selected cell is grounded. A second column line is coupled to the drain of the selected cell and a third column line is coupled to the drain of the adjacent cell. Simultaneously, a first potential is applied to the second column line to conditionally flow a read current through the selected cell while the second potential is applied to the third column line to shield the adjacent cell from parasitic current. To avoid disturbance of adjacent cells during programming, the array is effectively debiased utilizing intercolumn pass gates along with slow ramping of the selected column voltage.