Method of manufacturing non-volatile semiconductor memories, in which

Abstract

There is formed on a surface of a first conductivity type semiconductor substrate strip shaped first insulator separately extending in parallel with one another. A plurality of stacked gate structures, each comprising a second insulator, a floating gate, a third insulator, a control gate, a fourth insulator and an etching stopper having a slower etching speed than the fourth insulator, are formed on the substrate and the first insulator. Those portions of each first insulator that are located between the parallel extending gate structures and are present at prospective source regions are self-aligningly removed with using one end side of each gate structure as a part of a mask, so as to expose those portions of the substrate that are located at the prospective source regions. Impurities of a second conductivity type are self-aligningly introduced into each prospective source region with using one end side of each gate structure as a part of a mask to form a fifth insulator on a side wall of each gate structure. Impurities of the second conductivity type are self-aligningly introduced into each of prospective drain regions with using a drain side end of each gate structure as a part of a mask. Conductive layers are formed to contact with surfaces of the exposed drain regions and cover at least those parts of the fifth insulator that are laid on the walls at the drain regions of any two adjacent gate structures with corresponding one of the exposed drain regions between them. Sixth insulator is deposited on the resultant structure and are selectively removed with using the conductive layers as stoppers to make contact holes.