The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 1991

Filed:

Aug. 31, 1989
Applicant:
Inventors:

Shuji Kikuchi, Kanagawa, JP;

Yoshio Ouchida, Honjo, JP;

Ryohei Kamiya, Honjo, JP;

Assignees:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
371 27 ;
Abstract

To speed up the pattern generator which is a bottleneck for speedup of an LSI tester, a continuous address control information for generating addresses for continuous pattern memory read is generated at a speed 1/N (N is an optional number larger than 1) times the operation speed of the continuous address generator, and the address controller is divided into a 1st and a 2nd address controller. The two controllers are connected via a buffer memory to ensure the normal operation when the correspondence between address control instructions and patterns to be continuously read is not 1:N. Continuous address information generated by the 1st address controller is stored in the buffer memory. The second address controller, which actually generates continuous addresses, receives the continuous address information from the buffer memory, outputs the addresses to the pattern memory at a speed N times of the operation speed of the 1st address controller, and receives the next continuous address information from the buffer memory once again when the continuous address generation is finished to repeat the operation mentioned above.


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