The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 19, 1991
Filed:
Nov. 13, 1987
Louis N Hutter, Richardson, TX (US);
Mark E Gibson, Mesquite, TX (US);
Jeffrey P Smith, Plano, TX (US);
Shiu-Hang Yan, Richardson, TX (US);
Arnold C Conway, Garland, TX (US);
John P Erdeljac, Plano, TX (US);
James D Goon, Dallas, TX (US);
AnhKim Duong, Garland, TX (US);
Mary A Murphy, Richardson, TX (US);
Susan S Kearney, Tully, NY (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
An integrated circuit having PMOS, NMOS and NPN transistors is described for applications in which both digital and analog circuits are required. The integrated circuit is designed to allow standard CMOS cells to be used in the integrated circuit without redesign. A P+ substrate (48) is provided upon which a first P- epitaxy layer (46) is formed. N+ DUF regions (50,52) are provided for the PMOS and NPN transistors, respectively. The base region (68) is formed in an Nwell (58) by implantation and diffusion. Before diffusion, a nitride layer (70) is formed over the base (68) to provided an inert annealing thereof. The base diffusion and collector diffusion occurs before the CMOS channel stop and source/drain diffusions in order to prevent altering diffusion times for the MOS transistors.