Photolithographic method for manufacturing semiconductor wiring patterns

Abstract

A method for manufacturing semiconductor devices comprising the steps of forming a first wiring pattern including first and second lower layers on a semiconductor body, forming an insulation film which covers the first wiring pattern, forming a first hole of 1.5 .mu.m and a second hole of 3 .mu.m in first and second areas of the insulation film which lie over the first and second lower layers, forming a second wiring pattern having first and second upper layers respectively connected to the first and second lower layers via the first and second holes. In the method, the hole formation step includes the substeps of forming a resist film which covers the insulation film, forming a resist pattern by effecting the photolithographic process of exposing the insulation film to light by using a mask pattern having a first hole defining area of 1.5 .mu.m and a second hole defining area of 2.4 .mu.m, and etching the insulation film with the resist pattern used as a mask. The exposing light amount used in the resist pattern formation substep is previously determined so that the size of the first hole can be set equal to that of the first hole defining area, and the reduced amount of the second hole defining area is previously determined so that the size of the second hole obtained under the determined exposing light amount can be set to 3 .mu.m.