The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 14, 1990
Filed:
Jun. 03, 1988
Yoichi Tamaki, Kokubunji, JP;
Kiyoji Ikeda, Hachioji, JP;
Toru Nakamura, Tanashi, JP;
Akihisa Uchida, Tachikawa, JP;
Toru Koizumi, Tachikawa, JP;
Hiromichi Enami, Tachikawa, JP;
Satoru Isomura, Hamura, JP;
Shinji Nakajima, Hamura, JP;
Katsumi Ogiue, Hinode, JP;
Kaoru Ohgaya, Ohme, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
A multilayer semiconductor integrated circuit having a plurality of wiring layers in which at least the lines of a lower layer are extended on wiring channel regions arranged in a grid. Dummy pedestals are formed of the same conductive layer as that forming the lines of the lower layer and are arranged in the intersecting areas of the wiring channel regions where none of the lines of the lower layer is placed. A method of manufacturing such a semiconductor integrated circuit comprises steps of preparing dummy pedestal layout data for arranging the dummy pedestals in all the intersecting areas of the wiring channel regions and line layout data for forming the lines of the lower layer on predetermined wiring channels among all the wiring channel regions, and combining the dummy pedestal layout data and the line layout data by logical sum (OR).