Method of manufacturing a field effect transistor

Abstract

The invention relates to a method of manufacturing a field effect transistor comprising at the surface of a substrate of semi-insulating gallium arsenide W an active n-type active layer (102), on which is formed a gate electrode (G) of the Schottky type having at its lower part (15) the general form of a trapezoid, whose minor base is in contact with the active layer, then comprising on either side of the active layer a region of the n.sup.+ type (101 and 101') constituting the source and drain regions, of which the edges adjacent to the active layer are self-aligned with the edges of the major base of the trapezoid, and moreover comprising source (S) and drain (D) electrodes of the ohmic contact type formed at the surface of the regions of the n.sup.+ type. This transistor is characterized in that the gate electrode is composed of a weakly resistive metallic layer (105) and comprises an upper part (51) disposed on the major base of the trapezoid having a central metallic region (105) and a peripheral zone (106 ) of SiO.sub.2, which projects beyond the surface of the major base of the trapezoid, in that the source (S) and drain (D) electrodes (107) are self-aligned with the outer edges of the peripheral zone (106) of the gate, the latter being at right angles to a layer (103,104) of Si.sub.3 N.sub.4 separating the electrodes from each other.