The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 1989

Filed:

Apr. 22, 1988
Applicant:
Inventors:

Noboru Moriuchi, Tokyo, JP;

Yoshiki Yamaguchi, Tokyo, JP;

Toshihiko Tanaka, Tokyo, JP;

Norio Hasegawa, Hinode, JP;

Yoshifumi Kawamoto, Kanagawa, JP;

Shin-ichiro Kimura, Hachioji, JP;

Toru Kaga, Urawa, JP;

Tokuo Kure, Kokubunji, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
437 52 ; 437 38 ; 437 47 ; 437 60 ; 437228 ; 437235 ;
Abstract

A semiconductor memory wherein a memory cell region having a plurality of memory cells and has higher altitude from the surface of semiconductor substrate is formed in the recessed part of semiconductor substrate having the recessed part and projected part and a peripheral circuit region which is comparatively low from the surface of semiconductor substrate is formed to the projected part of semiconductor substrate.


Find Patent Forward Citations

Moriuchi, Noboru. (1989). Method of making a semiconductor memory device with recessed array region (U.S. Patent No. 4882289). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4882289

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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