The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 10, 1989
Filed:
Apr. 17, 1987
Koichiro Ishibashi, Tokyo, JP;
Osamu Minato, Tokyo, JP;
Toshiaki Masuhara, Tokyo, JP;
Yoshio Sakai, Kanagawa, JP;
Toshiaki Yamanaka, Houya, JP;
Naotaka Hashimoto, Hachioji, JP;
Shoji Hanamura, Kokubunji, JP;
Nobuyuki Moriwaki, Kodaira, JP;
Shigeru Honjyo, Hachioji, JP;
Kiyotsugu Ueda, Hachioji, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
Each of the memory cells in a SRAM includes two driver MOS transistors, two transfer gate MOS transistors and two load resistances. The gate electrode layers of the MOS transistors are formed from a first-level conductive layer provided on the surface of a semiconductor substrate. The source regions of the two driver MOS transistors in each memory cell are connected in common and further connected to a ground potential point through a second-level conductive layer. The two load resistances in each memory cell are formed from a third-level high-resistance material layer. The second-level conductive layer is formed from a low-resistance material layer. Thus the resistance of the sources of the two driver MOS transistors is lowered.