Cmos semiconductor device

Abstract

In the CMOS semiconductor device having an epitaxial layer, a trench with an appropriate depth is formed in the vicinity of a boundary between a range in which a MOS transistor is formed and a well range in which another MOS transistor is formed; the inner wall surface of the trench is covered with a thermal oxide film; and the trench is buried with a semiconductor substance, so that two CMOS transistors can be electrically isolated by the trench to increase the latch-up holding voltage beyond a supply voltage (e.g. 5 v). Therefore, the latch-up proof resistance can be increased to protect the device from noise which otherwise would break the device. Further, the trench depth is shallower than the low impurity atom concentration layer (epitaxial layer) or 3 .mu.m but deeper than a value obtained by subtracting 2 .mu.m from the above thickness or 3 .mu.m.