The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 1987

Filed:

Jun. 17, 1985
Applicant:
Inventors:

Masami Konaka, Kawasaki, JP;

Naoyuki Shigyo, Yokohama, JP;

Ryo Dang, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
2957 / ; 29571 ; 148D / ;
Abstract

A method of manufacturing a MOS device wherein a semiconductor substrate is selectively etched to form a groove in a field region and an element formation region surrounded by the groove such that an angle .theta. is formed between a wall of the groove and a first imaginary extension of a top surface of the element formation region, the angle .theta. satisfying the relation, 70.degree..ltoreq..theta..ltoreq.90.degree.. Then, a field insulating film is deposited in the groove, and a MOS transistor is formed in the element formation region. The element formation region has source, drain and channel regions of a field effect transistor therein and a gate electrode formed on a gate insulating film on the channel region. The gate electrode extends onto the surface portion of the field insulating film. The thickness of an upper portion of the field insulating film above a first imaginary extension of an interface between the gate insulating film and the gate electrode is formed smaller than that of a lower portion of the field insulating film below the first imaginary extension.


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