The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 1987

Filed:

Mar. 08, 1985
Applicant:
Inventors:

Franz Neppl, Munich, DE;

Ulrich Schwabe, Munich, DE;

Konrad Hieber, Bernau, DE;

Assignee:

Siemens Aktiengesellschaft, Berlin and Munich, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B05D / ; C23C / ;
U.S. Cl.
CPC ...
427 38 ; 427 85 ; 427 93 ;
Abstract

A method for manufacture of gate electrodes formed of double layers of metal silicides having a high melting point and doped polycrystalline silicon. The polycystalline silicon is deposited in undoped fashion before the metal silicide and the doping of the silicon is obtained through the production of the source/drain-zones through ion implantation and a subsequent high temperature step. The method permits the problem-free manufacture of polycide-gates with n.sup.+ - and p.sup.+ -polysilicon on a chip without increased technological expense. Planarization is facilitated through the thin gate layers. The method is used in the manufacture of highly integrated CMOS-circuits.


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