The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 27, 1986
Filed:
Dec. 10, 1984
Alexander H Owens, Pennington, NJ (US);
Mark A Halfacre, Horsham, PA (US);
Wing K Huie, North Wales, PA (US);
David S Pan, Doylestown, PA (US);
Solid State Scientific, Inc., Willow Grove, PA (US);
Abstract
A CMOS EPROM or the like is made wherein the basic memory device or EPROM device is an N-channel IGFET (insulated gate field effect transistor) having a control gate self-aligned with an underlying floating gate. The sources and drains of the EPROM devices as well as the sources and drains of peripheral N-channel transistors, are made by implanting with arsenic and with phosphorous. When heated, the faster diffusing phosphorous outruns, and extends from the bulk of, the arsenic so that these sources and drains extend slightly under the adjacent gate. This extension of the drain in the memory device enables a faster programming capability. A similar but oppositely directed lateral extension of all these sources and drains reduces the leakage to the substrate and reduces the chances of shorts to the substrate due to slightly misaligned metal to source and drain contacts.