The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 31, 1985
Filed:
Jun. 15, 1984
Applicant:
Inventors:
Christopher Slawinski, Dallas, TX (US);
Robert R Doering, Plano, TX (US);
Clarence W Teng, Plano, TX (US);
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
2957 / ; 2957 / ; 29578 ; 29580 ; 148-15 ; 148D / ; 148D / ; 148D / ; 156643 ; 357 49 ; 357 50 ;
Abstract
A sidewall-nitride isolation technology refines process control over lateral oxide encroachment by preventing any thinning of the nitride moat-masking layer during the nitride etch step which clears the sidewall nitride layer from the bottom of the etched recesses in silicon. This is done by initially patterning the moat regions in an oxide/nitride/oxide stack, rather than the nitride/oxide stack of the prior art.
Quick Actions:
Slawinski, Christopher. (1985). Integrated circuit fabrication method utilizing selective etching and (U.S. Patent No. 4561172). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4561172
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile