The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 10, 1985
Filed:
Jan. 29, 1982
George Perlegos, Fremont, CA (US);
Seeq Technology, Inc., San Jose, CA (US);
Abstract
An MOS memory cell (44) including an electrically-programmable and electrically-erasable storage device (46) fabricated on a semiconductor substrate (50) is disclosed. The storage device (46) is divided into sensing and programming sections (90, 92), each of which sections comprises vertically-aligned floating gate and program gate portions (62L, 62R, 72L, 72R) respectively formed from first and second electrically-conductive strips (62, 72). A tunneling region (60) is formed in the substrate (50) beneath the floating gate portion (62R) of the storage device programming section (92) and a thin tunnel dielectric (70) is interposed between the tunneling region (60) and the programming section floating gate portion (62R to facilitate tunneling of charge carriers therebetween. First and second source/drain regions (94, 96) physically isolated from the tunneling region (60) are established in the substrate (50) in alignment with the sensing section floating gate and program gate portions (62L, 72L). The memory cell (44) additionally includes a selection device (48) comprised of first and second field effect transistor structures (98, 104) which can be activated during memory cell read, program and erase operations to supply selected unipolar potentials to the tunneling region (60) and the second source/drain region (96) associated with the storage device sensing section.