The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 27, 1985
Filed:
Jul. 02, 1984
Applicant:
Inventors:
Mark T Bohr, Beaverton, OR (US);
Ken K Yu, Portland, OR (US);
Leo D Yau, Durham, OR (US);
Shyam G Garg, Beaverton, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
2957 / ; 29571 ; 2957 / ; 2957 / ; 29578 ; 29590 ; 148175 ; 148D / ; 148D / ; 148D / ; 148D / ; 148D / ; 156643 ; 156653 ; 156657 ; 1566591 ; 357 51 ; 357 54 ; 357 59 ; 357 236 ;
Abstract
A CMOS process is described which is particularly suited for forming dynamic memory cells. The cells are formed in an n-well and a single plate member formed from a first layer of polysilicon is used for the entire array. Unique etching of the first polysilicon layer prevents stringers from occurring when the second layer of polysilicon is deposited. A tri-layer dielectric is used for the capacitors in the array. Novel 'rear-end' processing is disclosed using a phosphorus doped glass.