Method of fabricating zener diodes

Abstract

A process for forming zener diodes from an IC structure having coextensive layers of gate silicon dioxide and polycrystalline silicon on a substrate and self-aligned with a diffused region in the substrate. A differential oxidation of the polycrystalline silicon and substrate silicon is followed in turn by a silicon dioxide etch to expose only the polycrystalline silicon layer. Thereafter, the exposed polycrystalline silicon is etched with an etchant that does not materially etch silicon dioxide. The exposed substrate is then subjected to an ion implantation, performed with an energy sufficient to locate the peak impurity concentration below the substrate surface, and a dose sufficient to moderately dope the area originally under the polycrystalline silicon electrode while reducing the effective concentration of the opposite impurity type dopant in the diffused region of the substrate. Residual silicon dioxide is now removed with an etchant that does not materially etch silicon; exposing the active area of the substrate. Annealing follows to heal implant and etching damage. The junction of the zener diode formed thereby is located below the substrate surface and displaced laterally from any area of etchant damage to provide stable and reproducible zener break-down characteristics.