Mosfet structure and process to form micrometer long source/drain spacing

Abstract

A method for fabricating a semiconductor integrated circuit structure having sub-micrometer gate length field effect transistor devices is described wherein a surface isolation pattern is formed in a semiconductor substrate which isolates regions of the semiconductor within the substrate from one another. Certain of these semiconductor regions are designated to contain field effect transistor devices. A first insulating layer such as silicon dioxide which is designated to be in part the gate dielectric layer of the field effect transistor devices is formed over the isolation pattern surface. Then a conductive layer, a second silicon dioxide layer, a first silicon nitride layer, a polycrystalline silicon layer and a second nitride layer are formed thereover. The multilayer structure is etched to result in a patterned polycrystalline silicon layer having substantially vertical sidewalls some of which sidewalls extend across certain of the device regions. A well controlled sub-micrometer thickness layer is formed on these vertical sidewalls by thermal oxidation of the polycrystalline silicon surfaces. The patterned layer is then removed which leaves the pattern of sub-micrometer thickness silicon dioxide sidewall layer portions of which extend across certain of the device regions. The sidewall layer is utilized as a mask in etching the first silicon nitride layer, the second silicon dioxide layer and the conductive layer to form the gate electrode of the field effect transistor devices in the conductive layer having the length of the sidewall coating. Ion implantation is then accomplished adjacent to the gate electrode to form the desired source/drain element for the field effect devices in the device regions. The conductive layer and resulting gate electrode may be composed of polycrystalline silicon metal silicide, polycide (a combination of layers of polycrystalline silicon and metal silicide) or the like.