The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 13, 1983
Filed:
May. 22, 1980
Jiro Oshima, Yokohama, JP;
Masaharu Aoyama, Yokohama, JP;
Seiji Yasuda, Yokohama, JP;
Toshio Yonezawa, Yokosuka, JP;
Tokyo Shibaura Denki Kabushiki Kaisha, Kawasaki, JP;
Abstract
A method for manufacturing a semiconductor device having a high breakdown voltage and a high reliability, comprises (a) forming on a semiconductor substrate an insulating layer having a diffusion window; (b) forming an impurity-doped poly-silicon layer on the insulating layer and on that portion of the semiconductor substrate which is exposed through the diffusion window; (c) forming an undoped poly-silicon layer on the impurity-doped poly-silicon layer; (d) thermally oxidizing the substrate with the insulating layer, impurity-doped poly-silicon layer and undoped poly-silicon layer, thus diffusing the impurity from the impurity-doped poly-silicon layer into the semiconductor substrate through the diffusion window and converting the undoped poly-silicon layer to a silicon oxide layer; (e) forming on the silicon oxide layer an oxidation-resisting mask layer in a desired pattern; and (f) thermally oxidizing the substrate with the insulating layer, impurity-doped poly-silicon layer, silicon oxide layer and mask layer, thus converting those portions of the impurity-doped poly-silicon layer which lie beneath those portions of the silicon oxide layer which are exposed through the mask layer to impurity-doped silicon oxide layers, whereby the remaining portions of the impurity-doped poly-silicon layer provide an interconnection electrode layer having a desired pattern.