The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 25, 1982

Filed:

Feb. 03, 1981
Applicant:
Inventor:

Sheau-Ming S Liu, Los Altos, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
29571 ; 2957 / ; 29578 ; 29590 ; 148-15 ; 148187 ;
Abstract

A process for forming self-aligned, metal plated substrate regions and polysilicon members is described. Oxide lips or borders are formed along the sides of the polysilicon members beneath a masking member. An oxide damaging ion bombardment is used to damage the oxide on the substrate, however, the oxide lips remain protected because of the overlying masking member. A controlled etch is used to remove the damaged oxide leaving the polysilicon member separated from adjacent regions by the oxide lips. A tungsten deposition is used to form metal plating over the exposed substrate regions and over the polysilicon member, however, no metal is formed over the oxide lips.


Find Patent Forward Citations

Liu, Sheau-Ming. (1982). Process for forming metal plated regions and lines in mos circuits (U.S. Patent No. 4330931). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4330931

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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