The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 24, 1981
Filed:
May. 07, 1979
Irving T Ho, Poughkeepsie, NY (US);
Jacob Riseman, Poughkeepsie, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for making highly dense, dielectrically isolated, U-shaped MOSFET. In a preferred method a monocrystalline silicon P substrate with a N+ layer thereon, a P layer on the N+ layer and a N+ layer on the P layer is provided. A pattern of U-shaped openings is formed in the body through to the P substrate by the reactively ion etching technique. This pattern of openings is filled with an insulator material, such as silicon dioxide. A conductive layer of N+ doped polycrystalline silicon is deposited on the bare surface of this silicon body. Openings are formed in the polycrystalline silicon over the silicon dioxide filled openings. A silicon dioxide layer is then grown by, for example, thermal oxidation over the polycrystalline silicon layer. Reactively ion etching is used to produce substantially U-shaped openings through the layers over the P substrate and into the P substrate to substantially bisect the regions of monocrystalline silicon. This etching step forms two storage cells in the monocrystalline silicon areas and a bit line for each column of cells in the polycrystalline silicon layer. A silicon dioxide gate insulator is grownon the monocrystalline silicon surfaces of the U-shaped openings by thermal oxidation in a suitable ambient. Conductively doped polycrystalline silicon is deposited in the U-shaped openings over the silicon dioxide gate insulator layer until the openings are filled and cover the surface of the body. The conductively doped polycrystalline silicon on the surface of the body is etched in a suitable pattern to produce the word lines of the random access memory device.