Charge injector transistor memory

Abstract

Disclosed is a dynamic memory cell storing digital information, particularly adapted for integrated semiconductor circuit fabrication. The circuit configuration has a bipolar transistor with information storage preferrably in the capacitance of the junctions, and a field effect transistor (FET) for selectively injecting charge into the capacitances. In integrated form, isolation is required only between columns of cells, a buried subcollector forming a common sense line for the entire column, while each of the base regions (also used as a first controlled region of the FET) requires no external contact at all. A further impurity region formed into each column of cells forms a second region of the FET and can be used as a bit line for the entire column. In one embodiment, separate contacts are provided for each of the emitter regions and each of the FET gate regions, while in another embodiment, only a single contact to both of the emitter region and FET gate region of each cell is required.