Semiconductor package and manufacturing method thereof

Abstract

A manufacturing method of a semiconductor package includes: laterally covering a first die and a TIV with an insulating encapsulation, where the first die includes a semiconductor substrate and a TSV penetrating through the semiconductor substrate; recessing the semiconductor substrate, where the TSV protrudes above the semiconductor substrate; forming a patterned mask layer on the insulating encapsulation and the TIV, where the patterned mask layer exposes the semiconductor substrate and the TSV; forming a passivation material layer on the first die and the patterned mask layer, where a sidewall of the patterned mask layer is exposed by the passivation material layer; removing the patterned mask layer along with a portion of the passivation material layer on the patterned mask layer to expose the insulating encapsulation and the TIV; and removing an excess portion of the passivation material layer on the TSV to form a passivation layer laterally covering the TSV.