The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2026

Filed:

Oct. 03, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hyunsoo Chung, Suwon-si, KR;

Younglyong Kim, Suwon-si, KR;

Taeyoung Lee, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 20/20 (2026.01); H10W 20/42 (2026.01); H10W 74/10 (2026.01); H10W 72/20 (2026.01); H10W 72/90 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 20/20 (2026.01); H10W 20/42 (2026.01); H10W 74/111 (2026.01); H10W 72/252 (2026.01); H10W 72/952 (2026.01); H10W 90/792 (2026.01);
Abstract

A semiconductor package includes a first semiconductor structure including a first semiconductor layer having a first active surface and a first circuit device thereon and a first inactive surface and first bonding layer; a second semiconductor structure on the first semiconductor structure and including a second semiconductor layer having a second active surface and second circuit device thereon and a second inactive surface, a second frontside bonding layer, and a second backside bonding layer on the second inactive surface; and a third semiconductor structure on the second semiconductor structure and including a third semiconductor layer having a third active surface including a third circuit device thereon and a third inactive surface, and a third bonding layer, wherein the first bonding layer is bonded to the second frontside bonding layer, and the third bonding layer is bonded to the second backside bonding layer.


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Chung, Hyunsoo. (2026). Semiconductor package (U.S. Patent No. 12796554). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12796554

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