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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12795935 B1

PDFFull Text
Date of Patent:
Nov. 10, 2026

Filed:

Oct. 04, 2023

Three-dimensional memory array with dual-level peripheral circuits and methods for forming the same

Applicant:

Sandisk Technologies, Inc., Milpitas, CA (US);

Inventors:

Masanori Tsutsumi, Yokkaichi, JP;

Kazutaka Yoshizawa, Yokkaichi, JP;

Hiroyuki Ogawa, Nagoya, JP;

Fumiaki Toyama, Cupertino, CA (US);

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:

THE MARBURY LAW GROUP PLLC

Primary Examiner:

Christine S Kim

Assistant Examiner:

Tyler J Wiegand

Int. Cl.
CPC ...
H10B 43/40 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/40 (2023.01); H10B 41/43 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/50 (2023.01); H10W 20/41 (2026.01); H10W 20/42 (2026.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
H10B 43/40 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/40 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/50 (2023.02); G11C 16/0483 (2013.01); H10B 41/10 (2023.02); H10B 41/43 (2023.02); H10B 43/10 (2023.02); H10W 20/42 (2026.01); H10W 20/435 (2026.01);
Abstract

A bonded assembly includes a memory die containing a three-dimensional memory array, a first logic die bonded to the memory die, a first peripheral circuit located in the logic die and configured to control operation of a first set of electrical nodes of the three-dimensional memory array, and a second peripheral circuit configured to control operation of a second set of electrical nodes of the three-dimensional memory array, where the second peripheral circuit is located at a different vertical level than the first peripheral circuit relative to the three-dimensional-memory array.

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Tsutsumi, Masanori. (2026). Three-dimensional memory array with dual-level peripheral circuits and methods for forming the same (U.S. Patent No. 12795935). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12795935

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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