Semiconductor package

Abstract

The reliability of stacked semiconductor packages may be improved via a semiconductor package including a first semiconductor chip including through silicon vias (TSVs) with respective upper conductive pads electrically connected to the TSVs, a second semiconductor chip on the first semiconductor chip with lower conductive pads on a lower surface of the second semiconductor chip, conductive bumps between the upper conductive pads and the lower conductive pads, and an interlayer adhesive layer between the first semiconductor chip and the second semiconductor chip. An interlayer space is between the first semiconductor chip and the second semiconductor chip and overlaps the first semiconductor chip and the second semiconductor chip in a vertical direction. The encapsulant extends into the interlayer space.