The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2026

Filed:

Jun. 30, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Stephen Morein, San Jose, CA (US);

Ravindranath Vithal Mahajan, Chandler, AZ (US);

Prashant Majhi, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 72/00 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 72/823 (2026.01);
Abstract

Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a plurality of vertically stacked dies; a trench of dielectric material through the plurality of vertically stacked dies; and a plurality of conductive vias extending through the trench of dielectric material, wherein individual ones of the plurality of conductive vias are electrically coupled to individual ones of the plurality of vertically stacked dies.


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Quick Actions:

Morein, Stephen. (2026). Microelectronic assemblies including stacked dies coupled by a through dielectric via (U.S. Patent No. 12787863). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12787863

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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