The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2026

Filed:

Jun. 06, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Jooi Wah Wong, Bukit Mertajam, MY;

Eng Huat Goh, Ayer Itam, MY;

Telesphor Kamgaing, Chandler, AZ (US);

Chee Kheong Yoon, Bayan Lepas, MY;

Min Suet Lim, Gelugor, MY;

Kavitha Nagarajan, Bangalore, IN;

Chu Aun Lim, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 20/41 (2026.01); G11C 11/4093 (2006.01);
U.S. Cl.
CPC ...
H10W 20/435 (2026.01); G11C 11/4093 (2013.01);
Abstract

Embodiments disclosed herein include package substrates. In an embodiment, a package substrate comprises a core, a first layer on the core, where the first layer comprises a first plane, a second layer on the first layer, where the second layer comprises first traces and second traces arranged in an alternating pattern, a third layer on the second layer, where the third layer comprises third traces and fourth traces arranged in an alternating pattern, and a fourth layer over the third layer, where the fourth layer comprises a second plane.


Find Patent Forward Citations

Quick Actions:

Wong, Jooi. (2026). On package interconnect architecture for high-speed memory (U.S. Patent No. 12787751). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12787751

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