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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12787428 B1

PDFFull Text
Date of Patent:
Nov. 03, 2026

Filed:

Dec. 20, 2022

Gate tie-down for top field effect transistor

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ruilong Xie, Niskayuna, NY (US);

Julien Frougier, Albany, NY (US);

Min Gyu Sung, Latham, NY (US);

Chanro Park, Clifton Park, NY (US);

Juntao Li, Cohoes, NY (US);

Assignee:

International Business Machines Corporation, Armonk, NY (US);

Attorneys:

Cantor Colburn LLP

Kristofer Haggerty

Primary Examiner:

David C Spalla

Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 21/822 (2006.01); H01L 21/8238 (2006.01); H01L 23/528 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); H10D 88/00 (2025.01); H10W 20/41 (2026.01);
U.S. Cl.
CPC ...
H10D 84/856 (2025.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 84/0167 (2025.01); H10D 84/0186 (2025.01); H10D 84/0188 (2025.01); H10D 84/038 (2025.01); H10D 88/01 (2025.01); H10W 20/427 (2026.01);
Abstract

A semiconductor device is provided. The semiconductor device includes a stacked field effect transistor (FET) structure. The stacked FET structure includes a bottom FET device, a top FET device overlying the bottom FET device, dielectric material interposed between the bottom FET device and the top FET device and a gate tie-down assembly of the top FET device extending through the bottom FET device.

Find Patent Forward Citations

Quick Actions:

Xie, Ruilong. (2026). Gate tie-down for top field effect transistor (U.S. Patent No. 12787428). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12787428

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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