The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2026

Filed:

Sep. 30, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sukru Yemenicioglu, Portland, OR (US);

Leonard P. Guler, Hillsboro, OR (US);

Tahir Ghani, Portland, OR (US);

Marni Nabors, Portland, OR (US);

Xinning Wang, Hillsboro, OR (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/83 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/47 (2025.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2026.01); H10D 84/03 (2025.01); H10W 10/00 (2026.01); H10W 10/17 (2026.01);
U.S. Cl.
CPC ...
H10D 84/83 (2025.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/47 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 84/0128 (2025.01); H10D 84/0151 (2025.01); H10D 84/038 (2025.01); H10W 10/014 (2026.01); H10W 10/17 (2026.01); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 84/0158 (2025.01); H10D 84/834 (2025.01);
Abstract

An integrated circuit includes a first device and a laterally adjacent second device. The first device includes a first body including semiconductor material extending from a first source region to a first drain region, and a first gate structure on the first body. The second device includes a second body including semiconductor material extending from a second source region to a second drain region, and a second gate structure on the second body. A gate cut including dielectric material is between and laterally separates the first gate structure and the second gate structure. The first body is separated laterally from the gate cut by a first distance, and the second body is separated laterally from the gate cut by a second distance. In an example, the first and second distances differ by at least 2 nanometers. In an example, the first and second devices are fin-based devices or gate-all-around devices.


Find Patent Forward Citations

Quick Actions:

Yemenicioglu, Sukru. (2026). Gate cut, with asymmetrical channel to gate cut spacing (U.S. Patent No. 12787422). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12787422

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