The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2026

Filed:

Jun. 29, 2023
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Congyong Zhu, Gilbert, AZ (US);

Philippe Renaud, Chandler, AZ (US);

Darrell Glenn Hill, Chandler, AZ (US);

Gregory David Hale, Chandler, AZ (US);

Colby Greg Rampley, Phoenix, AZ (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 64/01 (2025.01); H10D 64/00 (2025.01); H10D 84/01 (2026.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 64/021 (2025.01); H10D 64/111 (2025.01); H10D 84/0147 (2025.01); H10D 84/038 (2025.01); H10D 84/83 (2025.01);
Abstract

A transistor device and method of fabrication are provided, where the transistor device may include a semiconductor substrate, a first dielectric layer disposed on a surface of the semiconductor substrate, a second dielectric layer disposed directly on the first dielectric layer, a gate structure disposed directly on the surface of the semiconductor substrate, and a spacer structure. A first opening through the first dielectric layer and the second dielectric layer may correspond to a gate channel. Portions of the first dielectric layer and the second dielectric layer may be interposed directly between portions of the gate structure and the surface of the semiconductor substrate. The spacer structure may be disposed in the gate channel and interposed between the gate structure and the semiconductor substrate. The spacer structure may contact respective side surfaces of the first dielectric layer and the second dielectric layer that at least partially define the gate channel.


Find Patent Forward Citations

Quick Actions:

Zhu, Congyong. (2026). Transistors with dielectric spacers and methods of fabrication thereof (U.S. Patent No. 12787402). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12787402

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