The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2026

Filed:

Sep. 20, 2022
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Junjing Bao, San Diego, CA (US);

Xia Li, San Diego, CA (US);

Giridhar Nallapati, San Diego, CA (US);

Assignee:

QUALCOMM Incorproated, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 30/63 (2025.01); H10D 30/01 (2025.01); H10D 30/69 (2025.01); H10D 62/13 (2025.01); H10D 62/17 (2025.01); H10D 62/822 (2025.01); H10D 64/01 (2025.01); H10D 64/23 (2025.01); H10D 64/66 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 62/292 (2025.01); H10D 30/025 (2025.01); H10D 30/63 (2025.01); H10D 30/797 (2025.01); H10D 62/151 (2025.01); H10D 62/822 (2025.01); H10D 64/01 (2025.01); H10D 64/252 (2025.01); H10D 64/679 (2025.01); H10D 84/85 (2025.01);
Abstract

Vertical channel field-effect transistors (VCFETs) with reduced contact resistance and/or parasitic capacitance, and related fabrication methods. In exemplary aspects, to reduce contact resistance of the VCFET, an end portion of the vertical channel has a semiconductor structure that has an expanded width in the horizontal direction parallel to the substrate surface. This provides a greater area to form a contact for a source/drain to reduce contact resistance of the VCFET. To reduce the parasitic capacitance between the gate and a contact of the VCFET, the spacer includes one or more air gaps that form an air spacer(s) between the gate and the contact to reduce the overall average permittivity of the spacer. In one example, the air spacer(s) of the VCFET is elongated in the horizontal direction parallel to the substrate surface (and perpendicular to the vertical direction of the vertical channel) to further reduce the parasitic capacitance.


Find Patent Forward Citations

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Bao, Junjing. (2026). Vertical channel field effect transistor (vcfet) with reduced contact resistance and/or parasitic capacitance, and related fabrication methods (U.S. Patent No. 12787388). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12787388

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