Memory device with segmented sgd drain

Abstract

A variety of applications can include memory devices designed to provide enhanced gate-induced-drain-leakage (GIDL) current during memory erase operations. The enhanced operation can be provided by enhancing the electric field in the channel structures of select gate transistors to strings of memory cells at segmented drains of the select gate transistors. The segmented drains can have conductive fins integrated with the transistor channel structure and extending vertically from a top border of the transistor channel structure, where the conductive fins are separated from each other by non-conductive regions on the top border. The segmented drain can include portions extending downward below the top border. The transistor channel structures can be integrated with the channel structures of the pillars forming the strings of memory cells. Additional devices, systems, and methods are discussed.