The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2026

Filed:

Nov. 18, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Jorge Eduardo Parra Osorio, El Dorado Hills, CA (US);

Guei-Yuan Lueh, San Jose, CA (US);

Maxim Kazakov, San Diego, CA (US);

Fangwen Fu, Folsom, CA (US);

Supratim Pal, Folsom, CA (US);

Kaiyu Chen, San Jose, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); G06F 9/30 (2018.01); G06F 9/48 (2006.01); G06F 9/52 (2006.01); G06F 15/80 (2006.01);
U.S. Cl.
CPC ...
G06F 9/5027 (2013.01); G06F 9/30036 (2013.01); G06F 9/48 (2013.01); G06F 9/522 (2013.01); G06F 15/8046 (2013.01);
Abstract

An apparatus to facilitate cross-thread register sharing for matrix multiplication compute is disclosed. The apparatus includes matrix acceleration hardware comprising a plurality of data processing units, wherein the respective plurality of data processing units are to: receive a decoded instruction for a first thread having a first register space, wherein the decoded instruction is for a matrix multiplication operation and comprises an indication to utilize a second register space of a second thread for an operand of the decoded instruction for the first thread; access the second register space of the second thread to obtain data for the operand of the decoded instruction; and perform the matrix multiplication operation for the first thread using the data for the operand from the second register space of the second thread.


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Parra Osorio, Jorge. (2026). Cross-thread register sharing for matrix multiplication compute (U.S. Patent No. 12783309). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12783309

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